INTEL Logic Optimizing Compiler Utilization Report                      add.rpt
FIT Release [ 4.0 ] SID [ 268 ]


***** Design implemented successfully


******************************* ERROR REPORT *******************************


WARNING E7200-FITENGN: 4 Unused Input(s). They use a pin, but do not feed anything.
SIGNALS: UNUSED1, UNUSED2, UNUSED3, UNUSED4


****************************** PART DESCRIPTION ******************************


         1             7
         1      1      5
         _______________
     12 |       o       | 74
        |               |
        |               |
        |               |
        |               |
        |               |
        |               |
     32 |_______________| 54
         3             5
         3             3
            FX780_84

*** CMOS Device:  Ground unused inputs and I/Os ***
     VCC   = VCC power (3 or 5 volt)             
     VCCoX = VCC power for CFB I/Os
     GND   = Connect to GND plane                 
     VPP   = Connect to VPP signal, VCC, or leave unconnected.
             Do NOT connect to GND.
     gnd   = an unused input or I/O pin.  Ensure termination

 V - represents signal voltage          O - represents an Open Drain output

PIN SIGNAL      V O PIN SIGNAL      V O PIN SIGNAL      V O PIN SIGNAL      V O 

1   A5             |22  SUM4           |43  gnd            |64  gnd            |
2   VCCo1          |23  GND            |44  VCCo6          |65  GND            |
3   (CLK1)         |24  VCCo2          |45  (CLK2)         |66  VCCo5          |
4   (VPP)          |25  VCCo0/4        |46  GND            |67  VCCo3/7        |
5   A0             |26  VCC            |47  CLK            |68  VCC            |
6   A1             |27  SUM3           |48  SHIFT          |69  SUM1           |
7   A2             |28  CRY4           |49  IN             |70  CRY2           |
8   A3             |29  GND            |50  UNUSED1        |71  GND            |
9   A4             |30  SUM7           |51  UNUSED2        |72  SUM2           |
10  (TDO)          |31  gnd            |52  (TMS)          |73  CRY3           |
11  (TDI)          |32  gnd            |53  (TCK)          |74  CRY1           |
12  SUM0           |33  gnd            |54  gnd            |75  B4             |
13  B7             |34  gnd            |55  gnd            |76  B3             |
14  B6             |35  gnd            |56  gnd            |77  UNUSED3        |
15  B5             |36  gnd            |57  gnd            |78  UNUSED4        |
16  CRY7           |37  gnd            |58  gnd            |79  B2             |
17  GND            |38  GND            |59  GND            |80  GND            |
18  SUM6           |39  gnd            |60  gnd            |81  B1             |
19  CRY6           |40  gnd            |61  gnd            |82  B0             |
20  SUM5           |41  gnd            |62  gnd            |83  A7             |
21  CRY5           |42  gnd            |63  gnd            |84  A6             |


****************************** PIN ASSIGNMENTS ******************************

**OUTPUTS**

Signal       Pin   V   D  Type   PTerms  [nu,up,lo,nl]  Blk  MCell

A0           5            D      1       [ 0, 1, 0, 0]    0  0    
A1           6            D      1       [ 0, 1, 0, 0]    0  3    
A2           7            D      1       [ 0, 1, 0, 0]    0  5    
A3           8            D      1       [ 0, 1, 0, 0]    0  7    
A4           9            D      1       [ 0, 0, 1, 0]    0  9    
A5           1            D      1       [ 0, 1, 0, 0]    1  0    
A6           84           D      1       [ 0, 1, 0, 0]    1  1    
A7           83           D      1       [ 0, 1, 0, 0]    1  2    
B0           82           D      1       [ 0, 1, 0, 0]    1  3    
B1           81           D      1       [ 0, 1, 0, 0]    1  4    
B2           79           D      1       [ 0, 1, 0, 0]    1  5    
B3           76           D      1       [ 0, 1, 0, 0]    1  8    
B4           75           D      1       [ 0, 0, 1, 0]    1  9    
B5           15           D      1       [ 0, 1, 0, 0]    2  6    
B6           14           D      1       [ 0, 1, 0, 0]    2  7    
B7           13           D      1       [ 0, 1, 0, 0]    2  8    
SUM0         12           C      2       [ 0, 0, 1, 0]    2  9    
SUM1         69           C      4       [ 0, 1, 0, 0]    3  0    
SUM2         72           C      4       [ 0, 1, 0, 1]    3  5    
SUM3         27           C      4       [ 0, 1, 0, 0]    4  0    
SUM4         22           C      4       [ 0, 1, 0, 0]    2  0    
SUM5         20           C      4       [ 0, 1, 0, 1]    2  2    
SUM6         18           C      4       [ 0, 1, 0, 1]    2  4    
SUM7         30           C      4       [ 0, 1, 0, 1]    4  5    
CRY1         74           C      1       [ 0, 0, 1, 0]    3  9    
CRY2         70           C      3       [ 0, 1, 0, 1]    3  3    
CRY3         73           C      3       [ 0, 1, 0, 1]    3  7    
CRY4         28           C      3       [ 0, 1, 0, 1]    4  3    
CRY5         21           C      3       [ 0, 1, 0, 1]    2  1    
CRY6         19           C      3       [ 0, 1, 0, 1]    2  3    
CRY7         16           C      3       [ 0, 1, 0, 1]    2  5    


**INPUTS**

Signal         Pin  V  Level Blk

CLK            47               
SHIFT          48               
IN             49               
UNUSED1        50               
UNUSED2        51               
UNUSED3        77               
UNUSED4        78               


**UNUSED RESOURCES**

      Pin  Macrocell                     Pin  Macrocell

        -    IO01                          -    IO02                  
        -    IO04                          -    IO06                  
        -    IO08                          -    IO16                  
        -    IO17                          -    IO31                  
        -    IO32                          -    IO34                  
        -    IO36                          -    IO38                  
        -    IO41                          -    IO42                  
        -    IO44                          -    IO46                  
       31    IO47                          -    IO48                  
       32    IO49                         64    IO50                  
       63    IO51                         62    IO52                  
       61    IO53                         60    IO54                  
       58    IO55                         57    IO56                  
       56    IO57                         55    IO58                  
       54    IO59                         43    IO60                  
       42    IO61                         41    IO62                  
       40    IO63                         39    IO64                  
       37    IO65                         36    IO66                  
       35    IO67                         34    IO68                  
       33    IO69                          -    IO70                  
        -    IO71                          -    IO72                  
        -    IO73                          -    IO74                  
        -    IO75                          -    IO76                  
        -    IO77                          -    IO78                  
        -    IO79                          3    -       (CLK1      )  
       45    -       (CLK2      )  

       24  : 49  Totals unused


****************************** CFB INFORMATION ******************************



**CFB Descriptions**

 CFB #
 0                   1                   2                   3                  
--------------------------------------------------------------------------------
IO00  A0           |IO10  A5           |IO20  SUM4         |IO30  SUM1         |
IO03  A1           |IO11  A6           |IO21  CRY5         |IO33  CRY2         |
IO05  A2           |IO12  A7           |IO22  SUM5         |IO35  SUM2         |
IO07  A3           |IO13  B0           |IO23  CRY6         |IO37  CRY3         |
IO09  A4           |IO14  B1           |IO24  SUM6         |IO39  CRY1         |
                   |IO15  B2           |IO25  CRY7         |                   |
                   |IO18  B3           |IO26  B5           |                   |
                   |IO19  B4           |IO27  B6           |                   |
                   |                   |IO28  B7           |                   |
                   |                   |IO29  SUM0         |                   |


 CFB #
 4                   5                   6                   7                  
--------------------------------------------------------------------------------
IO40  SUM3         |                   |                   |                   |
IO43  CRY4         |                   |                   |                   |
IO45  SUM7         |                   |                   |                   |
                   |                   |                   |                   |
                   |                   |                   |                   |
                   |                   |                   |                   |
                   |                   |                   |                   |
                   |                   |                   |                   |
                   |                   |                   |                   |
                   |                   |                   |                   |


**CFB Control Signals**

CFB # 0 Controls
Signal                     Equation
------------               --------
Sync. Clock 1        :  -
Sync. Clock 2        :  -
Async. Clock 1 pterm : A4.ACLK


CFB # 1 Controls
Signal                     Equation
------------               --------
Sync. Clock 1        :  -
Sync. Clock 2        :  -
Async. Clock 1 pterm : B4.ACLK


CFB # 2 Controls
Signal                     Equation
------------               --------
Sync. Clock 1        :  -
Sync. Clock 2        :  -
Async. Clock 1 pterm : B7.ACLK




**CFB fanins**

         | CFB #
         |  0                1                2                3              
------------------------------------------------------------------------------
%0       | CLK.INT        | CLK.INT        | CRY4.FB        | CRY1.FB        |
%1       | SHIFT.INT      | SHIFT.INT      | A4.FB          | A1.FB          |
%2       | IN.INT         | A4.FB          | B4.FB          | B1.FB          |
%3       | A0.FB          | A5.FB          | CRY5.FB        | CRY2.FB        |
%4       | A1.FB          | A6.FB          | A5.FB          | A2.FB          |
%5       | A2.FB          | A7.FB          | B5.FB          | B2.FB          |
%6       | A3.FB          | B0.FB          | CRY6.FB        | A0.FB          |
%7       |                | B1.FB          | A6.FB          | B0.FB          |
%8       |                | B2.FB          | B6.FB          |                |
%9       |                | B3.FB          | CLK.INT        |                |
%10      |                |                | SHIFT.INT      |                |
%11      |                |                | A0.FB          |                |
%12      |                |                | B0.FB          |                |
%13      |                |                |                |                |
%14      |                |                |                |                |
%15      |                |                |                |                |
%16      |                |                |                |                |
%17      |                |                |                |                |
%18      |                |                |                |                |
%19      |                |                |                |                |
%20      |                |                |                |                |
%21      |                |                |                |                |
%22      |                |                |                |                |
%23      |                |                |                |                |


         | CFB #
         |  4                5                6                7              
------------------------------------------------------------------------------
%0       | CRY3.FB        |                |                |                |
%1       | A3.FB          |                |                |                |
%2       | B3.FB          |                |                |                |
%3       | CRY7.FB        |                |                |                |
%4       | A7.FB          |                |                |                |
%5       | B7.FB          |                |                |                |
%6       |                |                |                |                |
%7       |                |                |                |                |
%8       |                |                |                |                |
%9       |                |                |                |                |
%10      |                |                |                |                |
%11      |                |                |                |                |
%12      |                |                |                |                |
%13      |                |                |                |                |
%14      |                |                |                |                |
%15      |                |                |                |                |
%16      |                |                |                |                |
%17      |                |                |                |                |
%18      |                |                |                |                |
%19      |                |                |                |                |
%20      |                |                |                |                |
%21      |                |                |                |                |
%22      |                |                |                |                |
%23      |                |                |                |                |

***************************** DESIGN STATISTICS *****************************

    Inputs ...........  7
    Outputs .......... 31
    Active Pins (in+out) .... 38

           Combinatorial.... 15
           D flip-flops .... 16
           T flip-flops ....  0
         J/K (emulation) ...  0
    Total Macrocells ............ 31         Buried Macrocells ...  0
    (includes SRAM Macrocells ... 0 )

    Largest Product Term ...  4
    Macrocell Product Terms (1-16): 17, 1, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
    Total Product Terms >16       : 0

    DEVICE LISTED IN DESIGN: FX780_84
    STATUS:  OK
              ACTIVE              TOTAL       TOTAL
              PINS      MCELLS    PTERMS      DEVICE
              --------- --------- ---------   ---------
    FX780_84   38/62     31/80     13%          45%     

INTEL Logic Optimizing Compiler Utilization Report                      add.rpt
FIT Release [ 4.0 ] SID [ 268 ]

OPTIONS
    EXPAND = ON
    INVERSION = ON
    DT_SYNTHESIS = ON
    MINIMIZATION = ON
    FITTER_PINS = KEEP
    FITTER_PREV_PINS = OFF
    FITTER_ALGORITHM = NORMAL
    SECURITY = OFF

CHIP  add IFX780_84

PIN         47    CLK        
PIN         48    SHIFT      
PIN         49    IN         
PIN    [50:51]    UNUSED[1:2]
PIN    [77:78]    UNUSED[3:4]

PIN      [5:9]    A[0:4]     
PIN          1    A5         
PIN    [84:83]    A[6:7]     
PIN    [82:81]    B[0:1]     
PIN         79    B2         
PIN    [76:75]    B[3:4]     
PIN    [15:13]    B[5:7]     
PIN         12    SUM0       
PIN         69    SUM1       
PIN         72    SUM2       
PIN         27    SUM3       
PIN         22    SUM4       
PIN         20    SUM5       
PIN         18    SUM6       
PIN         30    SUM7       
PIN         74    CRY1       
PIN         70    CRY2       
PIN         73    CRY3       
PIN         28    CRY4       
PIN         21    CRY5       
PIN         19    CRY6       
PIN         16    CRY7       

EQUATIONS

A0.D := IN
A0.ACLK = CLK * SHIFT
A0.RSTF = GND
A0.SETF = GND
A0.TRST = VCC

A1.D := A0
A1.ACLK = CLK * SHIFT
A1.RSTF = GND
A1.SETF = GND
A1.TRST = VCC

A2.D := A1
A2.ACLK = CLK * SHIFT
A2.RSTF = GND
A2.SETF = GND
A2.TRST = VCC

A3.D := A2
A3.ACLK = CLK * SHIFT
A3.RSTF = GND
A3.SETF = GND
A3.TRST = VCC

A4.D := A3
A4.ACLK = CLK * SHIFT
A4.RSTF = GND
A4.SETF = GND
A4.TRST = VCC

A5.D := A4
A5.ACLK = CLK * SHIFT
A5.RSTF = GND
A5.SETF = GND
A5.TRST = VCC

A6.D := A5
A6.ACLK = CLK * SHIFT
A6.RSTF = GND
A6.SETF = GND
A6.TRST = VCC

A7.D := A6
A7.ACLK = CLK * SHIFT
A7.RSTF = GND
A7.SETF = GND
A7.TRST = VCC

B0.D := A7
B0.ACLK = CLK * SHIFT
B0.RSTF = GND
B0.SETF = GND
B0.TRST = VCC

B1.D := B0
B1.ACLK = CLK * SHIFT
B1.RSTF = GND
B1.SETF = GND
B1.TRST = VCC

B2.D := B1
B2.ACLK = CLK * SHIFT
B2.RSTF = GND
B2.SETF = GND
B2.TRST = VCC

B3.D := B2
B3.ACLK = CLK * SHIFT
B3.RSTF = GND
B3.SETF = GND
B3.TRST = VCC

B4.D := B3
B4.ACLK = CLK * SHIFT
B4.RSTF = GND
B4.SETF = GND
B4.TRST = VCC

B5.D := B4
B5.ACLK = CLK * SHIFT
B5.RSTF = GND
B5.SETF = GND
B5.TRST = VCC

B6.D := B5
B6.ACLK = CLK * SHIFT
B6.RSTF = GND
B6.SETF = GND
B6.TRST = VCC

B7.D := B6
B7.ACLK = CLK * SHIFT
B7.RSTF = GND
B7.SETF = GND
B7.TRST = VCC

SUM0 = A0 * /B0
     + /A0 * B0
SUM0.TRST = VCC

SUM1 = CRY1 * /A1 * /B1
     + CRY1 * B1 * A1
     + /CRY1 * A1 * /B1
     + /CRY1 * /A1 * B1
SUM1.TRST = VCC

SUM2 = CRY2 * /A2 * /B2
     + CRY2 * B2 * A2
     + /CRY2 * A2 * /B2
     + /CRY2 * /A2 * B2
SUM2.TRST = VCC

SUM3 = CRY3 * /A3 * /B3
     + CRY3 * B3 * A3
     + /CRY3 * A3 * /B3
     + /CRY3 * /A3 * B3
SUM3.TRST = VCC

SUM4 = CRY4 * /A4 * /B4
     + CRY4 * B4 * A4
     + /CRY4 * A4 * /B4
     + /CRY4 * /A4 * B4
SUM4.TRST = VCC

SUM5 = CRY5 * /A5 * /B5
     + CRY5 * B5 * A5
     + /CRY5 * A5 * /B5
     + /CRY5 * /A5 * B5
SUM5.TRST = VCC

SUM6 = CRY6 * /A6 * /B6
     + CRY6 * B6 * A6
     + /CRY6 * A6 * /B6
     + /CRY6 * /A6 * B6
SUM6.TRST = VCC

SUM7 = CRY7 * /A7 * /B7
     + CRY7 * B7 * A7
     + /CRY7 * A7 * /B7
     + /CRY7 * /A7 * B7
SUM7.TRST = VCC

CRY1 = A0 * B0
CRY1.TRST = VCC

CRY2 = A1 * B1
     + A1 * CRY1
     + B1 * CRY1
CRY2.TRST = VCC

CRY3 = A2 * B2
     + A2 * CRY2
     + B2 * CRY2
CRY3.TRST = VCC

CRY4 = A3 * B3
     + A3 * CRY3
     + B3 * CRY3
CRY4.TRST = VCC

CRY5 = A4 * B4
     + A4 * CRY4
     + B4 * CRY4
CRY5.TRST = VCC

CRY6 = A5 * B5
     + A5 * CRY5
     + B5 * CRY5
CRY6.TRST = VCC

CRY7 = A6 * B6
     + A6 * CRY6
     + B6 * CRY6
CRY7.TRST = VCC

